lv1145b lvds series 6 pad leadless surface mount oscillator low voltage differential signal output with enable/disable 10.00 mhz ? 650.00 mhz standard specifications overall frequency stability lv1145b: 50 ppm, lv1144b: 25 ppm, lv1120b: 20 ppm over operating temp. range operating temperature range 0 to +80 c is standard, can be extended to - 40 to +85 c operable supply voltage (vcc) 3.3 v 5 % standard, 5.0 v 10 % also available (2.5 v different package) part numbering guide 1.43 v typical and 1.60 v maximum with output enabled (100 o hm load) see test circuit #6 0.90 v minimum and 1.10 v typical with output enabled (100 o hm load) see tc #6 high level output voltage low level output voltage consult factory for available frequencies and specs. not all options available for all frequencies. a special part numbe r may be assigned. frequency stability is inclusive of frequency shifts due to calibration, temperature, supply voltage, shock, vibration a nd load (425) 776 - 1880, fax: (425) 776 - 2760, ple - sales@pletronics.com, www.pletronics.com 5 pl tronics, inc. model frequency stability 45 = 50 ppm lv11 = pin 1 n.c. lv33 = pin 1 e/d lv37 = pin 1 e/d 44 = 25 ppm frequency in mhz special specifications (choose all that apply) e: extended operating temp range (-40 to +85 c) v: supply voltage of 3.3 volts 5 % y: supply voltage of 5.0 volts 10%, w: supply voltage of 2.5 volts 5% (different package) lv11 45 b v - 70.0m - xxx (internal code or blank) 20 = 20 ppm output leakage current 10 ua maximum with output disabled differential output voltage offset voltage 247 v minimum, 330 v typical and 454 v maximum with output enabled (100 ohm load) see tc #6 1.125 v minimum, 1.25 v typical and 1.375 v maximum with ou tput enabled (100 ohm load) see tc #6 50 ma max < 200 mhz, 60 ma max < 500 mhz, 70 ma max 500 mhz and above 20 ma max < 200 mhz, 30 ma max < 500 mhz, 40 ma max 500 mhz and above supply current (icc) enabled 0.7 vcc minimum at enable / disable pin 0.3 vcc maximum at enable / disable pin high level input voltage low level input voltage output enable time 200 ns maximum high level input current low level input current -20 ua maximum at enable / disable pin = 0.7 vcc -200 ua maximum at enable / disable pin = 0 v 200 ns maximum output disable time supply current (icc) disabled rms jitter enable / disable pin: 1.0 ps max at12 khz to 20 mhz from the output symmetry (dc) rise and fall time (tr & tf) 45/55% measured at 0 c <= ta <= 70 c, 40/60% measured at ta < 0 c and ta > 70 c 1.0 ns max at 20% to 80% output swing (100 ohm load) see tes t circuit #6 and waveform #2 packaging tube or 24mm tape 16mm pitch consult factory for higher frequencies pl tronics , inc. 19013 36th ave. w, suite h lynnwood, wa 98036 usa manufacturer of high quality frequency control products . portions of the part number that appear after the frequency may not be marked on part (c of c provided) jun 2004 the enable / disable pin has an internal pull up and if the pin is not connected the oscilaltor is enabled. pletronics s trongly recommends connecting the enable / disable pin to vcc, if the oscillato r is to be enabled at all times. in the disable condition, t he output becomes a high impedance. pecl, lvds, ocxo page 1 - 7
lv1145b lvds series mechanical: not to scale inches (mm) solder pads (425) 776 - 1880, fax: (425) 776 - 2760, ple - sales@pletronics.com, www.pletronics.com 5a pl tronics, inc. due to part size and factory abilities, part marking may var y from lot to lot and may contain our part number or an inte rnal code. pl tronics , inc. 19013 36th ave. w, suite h lynnwood, wa 98036 usa manufacturer of high quality frequency control products . jun 2004 0.055 (1.4) 0.200 (5.08) 1 3 4 2 5 6 0.228 (5.8) 0.118 (3.0) 0 .145 (3.68) 0.400 (10.16) max 0.560 (14.23) max 0.125 (3.17) max 0.200 (5.08) 1 2 3 4 5 6 1 n.c. 2 e/d 3 gnd 4 vod+ 5 vod- 6 vcc pin signal 1 e/d 2 n.c. 3 gnd 4 vod+ 5 vod- 6 vcc pin signal 1 e/d 2 e/d 3 gnd 4 vod+ 5 vod- 6 vcc pin signal lv1145b lv3345b lv3745b see page 6 for layout guidelines 3.3 v and 5.0 v package 2.5 v package due to part size and factory abilities, part marking may var y from lot to lot and may contain our part number or an internal code. lv11bx 100.000m ple ev yywwx marking example and explanation lv11b = model code x = frequency stability frequency in mhz ple = pletronics ev = applicable specs (some internal) yywwx = date code 0.055 (1.4) 0.200 (5.08) 1 3 4 2 5 6 0.228 (5.8) 0.118 (3.0) 0 .145 (3.68) 0.400 (10.16) max 0.560 (14.23) max 0.125 (3.17) max 0.200 (5.08) 1 2 3 4 5 6 1 n.c. 2 e/d 3 gnd 4 vod+ 5 vod- 6 vcc pin signal 1 e/d 2 n.c. 3 gnd 4 vod+ 5 vod- 6 vcc pin signal 1 e/d 2 e/d 3 gnd 4 vod+ 5 vod- 6 vcc pin signal lv1145b lv3345b lv3745b 0.055 (1.4) 0.200 (5.08) 1 3 4 2 5 6 0.228 (5.8) 0.118 (3.0) 0.040 (1.02) 0.238 (6.05) 0.108 (2.75) max 0.200 (5.08) 0.040 (1.02) 1 2 3 2 1 3 4 5 6 4 6 5 0.356 (9.04) top view 0.324 (8.23) 0.059 (1.50) 0 .145 (3.68)
mar 2004 (425) 776 - 1880, fax: (425) 776 - 2760, ple - sales@pletronics.com, www.pletronics.com 6 pl tronics, inc. pecl and lvds layout guidelines pl tronics , inc. 19013 36th ave. w, suite h lynnwood, wa 98036 usa manufacturer of high quality frequency control products . top side bypass bottom side bypass multi layer bypass 0.055 (1.4) 0.100 (2.54) 0.200 (5.08) 0 .185 (4.7) 0 .087 (2.2) solder pad layout which accommodates all pecl surface mount devices 'b pkg' 5 x7 suggested pcb layouts the output line should be designed with proper characteristi c impedance. pletronics recommends laying out for the larger 'b package' with pads long enough to accept the smaller 5 x 7mm device. this permits the best option for alternate sources of device. pletronics also recommends connecting pin 1 and pin 2 together on the models with q & qn out on pins 4 & 5. this allows having e/d on either pin 1 or pin 2. for optimum jitter performance, pletronics recommends: a ground plane under the device with any other signals below the ground plane minimize other rf signals near device no large transient signals (both current and voltage) should be routed under the device do not layout near a large magnetic field such as a high fre quency switching power supply do not place near piezoelectric buzzers or mechancial fans 250 200 150 100 50 seconds 215 c 10 c 10 seconds max 260 c max 120 to 160 seconds 175 c 10 c t rise= 4 degree/second max temperature c reflow cycle for lead free processing pecl, lvds, ocxo page 1 - 7
mar 2004 (425) 776 - 1880, fax: (425) 776 - 2760, ple - sales@pletronics.com, www.pletronics.com 6a pl tronics, inc. pecl and lvds layout guidelines continued pl tronics , inc. 19013 36th ave. w, suite h lynnwood, wa 98036 usa manufacturer of high quality frequency control products . vcc vcc - 2.00 v gnd out vcc oscillator vcc gnd out vcc oscillator pecl terminations: lvds terminations: mixed system power supply: 50 ohm vcc gnd out vcc oscillator r load vcc gnd q out qn out vcc oscillator 100 ohm r1 r2 suggested terminations for 50 ohm impedance matched terminat ion simple termination for non impedance matched termination vcc 5.0 v 3.3 v 2.5 v r1 82 ohm 130 ohm 249 ohm vcc 5.0 v 3.3 v 2.5 v r load 274 ohm 147 ohm 86.6 ohm r2 130 ohm 82 ohm 61.9 ohm thevenin equivalent termination design pcb traces for 50 ohm characteristic impedance to use multiple supply voltages requires level translation. direct circuit connection is not valid. mixed supply voltages are allowed. no translation is necessa ry. (ecl is returned to the most positive supply and this is common to all circuits) mixed supply voltages are allowed. lvds signal levels are po wer supply independent. 3.3 v lvds oscillators properly interface 2.5 v logic arrays for example. pecl ecl lvds
|
